library ieee; use work.ucore_package.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity ucore_regio is port ( -- global clk : in std_logic; reset : in std_logic; -- in stall_read : in std_logic; stall_write : in std_logic; decode_opcode : in opcode_t; decode_rc : in std_logic_vector(2 downto 0); decode_rb : in std_logic_vector(2 downto 0); decode_ra : in std_logic_vector(2 downto 0); decode_imm : in std_logic_vector(15 downto 0); decode_rc_we : in std_logic; decode_imm_a : in std_logic; alu_rc_we : in std_logic; alu_rc : in std_logic_vector(2 downto 0); alu_data_c : in std_logic_vector(15 downto 0); -- out reg_data_b : out std_logic_vector(15 downto 0); reg_data_a : out std_logic_vector(15 downto 0); reg_rc : out std_logic_vector(2 downto 0); reg_rc_we : out std_logic; reg_opcode : out opcode_t; reg_simm : out std_logic_vector(15 downto 0) ); end entity; architecture rtl of ucore_regio is begin -- read / write reg process(clk) type regs_t is array(0 to 7) of std_logic_vector(15 downto 0); variable regs : regs_t := (others => (others => '0')); begin if rising_edge(clk) then -- ucore stage 5 if stall_write = '0' then -- write part if alu_rc_we = '1' then regs(conv_integer(alu_rc)) := alu_data_c; end if; end if; -- ucore stage 3 if stall_read = '0' then -- default reg_opcode <= decode_opcode; -- read part reg_data_b <= regs(conv_integer(decode_rb)); reg_data_a <= regs(conv_integer(decode_ra)); if decode_imm_a = '1' then reg_data_a <= decode_imm; end if; reg_rc <= decode_rc; reg_rc_we <= decode_rc_we; reg_simm <= decode_imm; end if; if reset = '1' then reg_rc_we <= '0'; reg_opcode <= ope_nop; --reg_simm <= (others => '0'); end if; end if; end process; end rtl;