library ieee; use work.ucore_package.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity compares is port ( -- data in b : in std_logic_vector(15 downto 0); a : in std_logic_vector(15 downto 0); -- data out cmpeq_res : out std_logic; cmplo_res : out std_logic; cmplos_res : out std_logic; cmple_res : out std_logic; cmples_res : out std_logic ); end entity; architecture rtl of compares is begin cmpeq_res <= '1' when b = a else '0'; cmplo_res <= '1' when b < a else '0'; cmplos_res <= '1' when (signed(b) < signed(a)) else '0'; cmple_res <= '1' when b <= a else '0'; cmples_res <= '1' when (signed(b) <= signed(a)) else '0'; end rtl;