library ieee; use work.ucore_package.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity bit_field is port ( -- data in b : in std_logic_vector(15 downto 0); a : in std_logic_vector(15 downto 0); -- data out bffo_res : out std_logic_vector(15 downto 0); bffo_t : out std_logic; bset_res : out std_logic_vector(15 downto 0); bclr_res : out std_logic_vector(15 downto 0); extr_t : out std_logic ); end entity; architecture rtl of bit_field is begin process(a,b) begin -- bffo (bit find first one) bffo_t <= '0'; -- default bffo_res <= x"0010"; -- default for i in 15 downto 0 loop if a(i) = '1' then bffo_res <= conv_std_logic_vector(i,16); bffo_t <= '1'; exit; -- stop loop end if; end loop; -- bset (bit set) bset_res <= b; bset_res(conv_integer(a(3 downto 0))) <= '1'; -- bclr (bit clear) bclr_res <= b; bclr_res(conv_integer(a(3 downto 0))) <= '0'; -- extr (extract bit) extr_t <= b( conv_integer(a(3 downto 0))); end process; end rtl;