library ieee; use work.bus_package.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity mem_sdram_MODELSIM is port ( -- global clk : in std_logic; reset : in std_logic; -- SDRAM DRAM_ADDR : out std_logic_vector(12 downto 0); DRAM_BA : out std_logic_vector(1 downto 0); DRAM_CAS_N : out std_logic; DRAM_CS_N : out std_logic; DRAM_DQ : inout std_logic_vector(31 downto 0); DRAM_DQM : out std_logic_vector(3 downto 0); DRAM_RAS_N : out std_logic; DRAM_WE_N : out std_logic; -- recive ports to_sdram_data : in sdram_n_data_t; to_sdram_busy : in sdram_n_busy_t; to_sdram_ack : out sdram_n_ack_t; -- send ports from_sdram_rclk : in sdram_rclk_t; from_sdram_data : out sdram_n_data_t; from_sdram_busy : out sdram_n_busy_t; from_sdram_ack : in sdram_n_ack_t ); end entity; architecture rtl of mem_sdram_MODELSIM is -- fifo for recive --component fifo_max -- PORT -- ( -- clock : IN STD_LOGIC ; -- data : IN STD_LOGIC_VECTOR (71 DOWNTO 0); -- rdreq : IN STD_LOGIC ; -- sclr : IN STD_LOGIC ; -- wrreq : IN STD_LOGIC ; -- empty : OUT STD_LOGIC ; -- full : OUT STD_LOGIC ; -- q : OUT STD_LOGIC_VECTOR (71 DOWNTO 0); -- usedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) -- ); --end component; component sc_fifo_usedw GENERIC ( FIFO_DEPTH : natural; FIFO_WIDTH : natural; FIFO_SHOWAHEAD : string; FIFO_USERAM : string; FIFO_USEDWWIDTH : natural ); PORT ( clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (FIFO_WIDTH-1 DOWNTO 0); rdreq : IN STD_LOGIC ; sclr : IN STD_LOGIC ; wrreq : IN STD_LOGIC ; empty : OUT STD_LOGIC ; full : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (FIFO_WIDTH-1 DOWNTO 0); usedw : OUT STD_LOGIC_VECTOR (FIFO_USEDWWIDTH-1 DOWNTO 0) ); end component; signal buf_data : STD_LOGIC_VECTOR (71 DOWNTO 0) := (others => '0'); signal buf_rdreq : STD_LOGIC := '0'; signal buf_wrreq : STD_LOGIC := '0'; signal buf_empty : STD_LOGIC := '0'; signal buf_full : STD_LOGIC := '0'; signal buf_dummy : STD_LOGIC := '0'; signal buf_q : STD_LOGIC_VECTOR (71 DOWNTO 0) := (others => '0'); signal buf_usedw : STD_LOGIC_VECTOR (7 DOWNTO 0) := (others => '0'); -- dcfifo (for send) --component dcfifo_min IS -- PORT -- ( -- aclr : IN STD_LOGIC := '0'; -- data : IN STD_LOGIC_VECTOR (71 DOWNTO 0); -- rdclk : IN STD_LOGIC ; -- rdreq : IN STD_LOGIC ; -- wrclk : IN STD_LOGIC ; -- wrreq : IN STD_LOGIC ; -- q : OUT STD_LOGIC_VECTOR (71 DOWNTO 0); -- rdempty : OUT STD_LOGIC ; -- wrusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) -- ); --END component; component dc_fifo IS GENERIC ( FIFO_DEPTH : natural; FIFO_WIDTH : natural; FIFO_SHOWAHEAD : string; FIFO_USEDWWIDTH : natural; FIFO_SYNCSTAGES : natural ); PORT ( aclr : IN STD_LOGIC := '0'; data : IN STD_LOGIC_VECTOR (FIFO_WIDTH-1 DOWNTO 0); rdclk : IN STD_LOGIC ; rdreq : IN STD_LOGIC ; wrclk : IN STD_LOGIC ; wrreq : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (FIFO_WIDTH-1 DOWNTO 0); rdempty : OUT STD_LOGIC ; wrusedw : OUT STD_LOGIC_VECTOR (FIFO_USEDWWIDTH-1 DOWNTO 0) ); END component; -- type send_xn_data_t is array(0 to mem_sdram_reciver_count-1) of STD_LOGIC_VECTOR (71 DOWNTO 0); type send_xn_wrreq_t is array(0 to mem_sdram_reciver_count-1) of STD_LOGIC; type send_xn_wrfull_t is array(0 to mem_sdram_reciver_count-1) of STD_LOGIC; type send_xn_wrusedw_t is array(0 to mem_sdram_reciver_count-1) of STD_LOGIC_VECTOR (7 DOWNTO 0); -- signal send_xn_data : send_xn_data_t := (others => (others => '0')); signal send_xn_wrreq : send_xn_wrreq_t := (others => '0'); signal send_xn_wrfull : send_xn_wrfull_t := (others => '0'); signal send_xn_wrusedw : send_xn_wrusedw_t := (others => (others => '0')); -- signal rs0_push : std_logic := '0'; signal rs0_data : port_struct := fill_port('0'); -- signal delay_it : std_logic := '0'; begin -- delay (to sim sdram charge/refresh etc.) process(clk) variable counter : integer := 0; begin if rising_edge(clk) then if counter = 4 then counter := 0; delay_it <= '0'; else counter := counter + 1; delay_it <= '1'; end if; end if; end process; -- dont care DRAM_ADDR <= (others => '0'); DRAM_BA <= (others => '0'); DRAM_CAS_N <= '0'; DRAM_CS_N <= '0'; DRAM_DQ <= (others => '0'); DRAM_DQM <= (others => '0'); DRAM_RAS_N <= '0'; DRAM_WE_N <= '0'; -- recive fifo recive_buffer : sc_fifo_usedw generic map ( FIFO_DEPTH => 256, FIFO_WIDTH => 72, FIFO_SHOWAHEAD => "ON", FIFO_USERAM => "ON", FIFO_USEDWWIDTH => 8 ) port map ( clk, buf_data, buf_rdreq, reset, buf_wrreq, buf_empty, buf_dummy, buf_q, buf_usedw ); process(clk) variable wor : std_logic := '0'; begin if rising_edge(clk) then wor := '0'; for i in 0 to mem_sdram_reciver_count-1 loop wor := wor or send_xn_wrfull(i); end loop; if buf_usedw >= x"f" then -- buf_full <= '1'; else buf_full <= '0';-- or wor; end if; end if; end process; -- recive ack process(all) begin for i in 0 to mem_sdram_reciver_count-1 loop to_sdram_ack(i) <= '0'; end loop; if reset = '0' then for i in 0 to mem_sdram_reciver_count-1 loop if to_sdram_busy(i) = '0' and buf_full = '0' then to_sdram_ack(i) <= '1'; exit; -- stop loop end if; end loop; end if; end process; process(clk) variable t_data : port_struct := fill_port('0'); begin if rising_edge(clk) then -- default buf_wrreq <= '0'; --buf_data <= to_sdram_data(0); -- if reset = '1' then -- else for i in 0 to mem_sdram_reciver_count-1 loop if to_sdram_busy(i) = '0' and buf_full = '0' then t_data := raw_to_port(to_sdram_data(i)); t_data.id := conv_std_logic_vector(i,6); -- store id buf_data <= port_to_raw(t_data); buf_wrreq <= '1'; exit; -- stop loop end if; end loop; end if; end if; end process; -- buffer fifo read request process(all) begin buf_rdreq <= '0'; if reset = '0' and buf_empty = '0' and delay_it = '0' then buf_rdreq <= '1'; -- ack end if; end process; process(clk) variable buf_in : port_struct := fill_port('0'); variable buf_out : port_struct := fill_port('0'); type memory_t is array(0 to 65535) of std_logic_vector(15 downto 0); variable memory : memory_t := (others => (others => '0')); variable q : std_logic_vector(31 downto 0); variable iaddress : integer; begin if rising_edge(clk) then -- default for i in 0 to mem_sdram_reciver_count-1 loop send_xn_wrreq(i) <= '0'; end loop; -- if reset = '1' then else if buf_empty = '0' and delay_it = '0' then buf_in := raw_to_port(buf_q); iaddress := conv_integer(buf_in.address and x"0000ffff"); if buf_in.we = '1' then -- write if buf_in.dmode = '1' then -- 16 bit memory(iaddress) := buf_in.data(15 downto 0); else -- 32 bit memory(iaddress) := buf_in.data(15 downto 0); memory(iaddress+1) := buf_in.data(31 downto 16); end if; else -- read if buf_in.dmode = '1' then -- 16 bit if buf_in.address(0) = '1' then -- l q := x"0000" & memory(iaddress)(15 downto 0); end if; else -- 32 bit q := memory(iaddress) & memory(iaddress+1); end if; send_xn_wrreq(conv_integer(buf_in.id)) <= '1'; -- push end if; end if; end if; -- set to all fifo inputs (send_xn_wrreq arbit write) for i in 0 to mem_sdram_reciver_count-1 loop buf_out.data := q; buf_out.address := buf_in.address; -- it is important to resend address (hcore will reselect) send_xn_data(i) <= port_to_raw(buf_out); end loop; end if; end process; -- full generate process(clk) begin for i in 0 to mem_sdram_reciver_count-1 loop if rising_edge(clk) then if send_xn_wrusedw(i) >= x"fb" then -- fb send_xn_wrfull(i) <= '1'; else send_xn_wrfull(i) <= '0'; end if; end if; end loop; end process; ----------------------------------------------------------------------------------------------------------- ---- SEND DATA ----------------------------------------------------------------------------------------------------------- dcfifo_loop : for i in 0 to mem_sdram_reciver_count-1 generate dcfifo : dc_fifo generic map ( FIFO_DEPTH => 256, FIFO_WIDTH => 72, FIFO_SHOWAHEAD => "ON", FIFO_USEDWWIDTH => 8, FIFO_SYNCSTAGES => 3 ) port map ( '0', send_xn_data(i), from_sdram_rclk(i), -- read with component clk from_sdram_ack(i), clk, -- write with clk send_xn_wrreq(i), from_sdram_data(i), from_sdram_busy(i), send_xn_wrusedw(i) ); end generate; end rtl;