library altera; use altera.altera_europa_support_lib.all; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; package bus_package is type port_struct is record data : std_logic_vector(31 downto 0); -- 32 address : std_logic_vector(31 downto 0); -- 32 dmode : std_logic; -- 1 we : std_logic; -- 1 id : std_logic_vector(5 downto 0); -- 6 (only used for internal processing [buffer fifos]) -- = 72 end record; -- mem flash constant mem_flash_reciver_count : integer := 1; type flash_n_data_t is array(0 to mem_flash_reciver_count-1) of std_logic_vector(71 downto 0); type flash_n_busy_t is array(0 to mem_flash_reciver_count-1) of std_logic; type flash_n_ack_t is array(0 to mem_flash_reciver_count-1) of std_logic; type flash_rclk_t is array(0 to mem_flash_reciver_count-1) of std_logic; -- mem sram constant mem_sram_reciver_count : integer := 3; type sram_n_data_t is array(0 to mem_sram_reciver_count-1) of std_logic_vector(71 downto 0); type sram_n_busy_t is array(0 to mem_sram_reciver_count-1) of std_logic; type sram_n_ack_t is array(0 to mem_sram_reciver_count-1) of std_logic; type sram_rclk_t is array(0 to mem_sram_reciver_count-1) of std_logic; -- mem sdram constant mem_sdram_reciver_count : integer := 5; type sdram_n_data_t is array(0 to mem_sdram_reciver_count-1) of std_logic_vector(71 downto 0); type sdram_n_busy_t is array(0 to mem_sdram_reciver_count-1) of std_logic; type sdram_n_ack_t is array(0 to mem_sdram_reciver_count-1) of std_logic; type sdram_rclk_t is array(0 to mem_sdram_reciver_count-1) of std_logic; -- ucore constant ucore_reciver_count : integer := 4; -- uctrl constant uctrl_reciver_count : integer := 2; -- sd card ctrl constant mem_sd_card_ctrl_reciver_count : integer := 1; type sd_ctrl_n_data_t is array(0 to mem_sd_card_ctrl_reciver_count-1) of std_logic_vector(71 downto 0); type sd_ctrl_n_busy_t is array(0 to mem_sd_card_ctrl_reciver_count-1) of std_logic; type sd_ctrl_n_ack_t is array(0 to mem_sd_card_ctrl_reciver_count-1) of std_logic; type sd_ctrl_rclk_t is array(0 to mem_sd_card_ctrl_reciver_count-1) of std_logic; constant mem_sd_card_data_reciver_count : integer := 2; type sd_data_n_data_t is array(0 to mem_sd_card_data_reciver_count-1) of std_logic_vector(71 downto 0); type sd_data_n_busy_t is array(0 to mem_sd_card_data_reciver_count-1) of std_logic; type sd_data_n_ack_t is array(0 to mem_sd_card_data_reciver_count-1) of std_logic; type sd_data_rclk_t is array(0 to mem_sd_card_data_reciver_count-1) of std_logic; -- hcores constant hcore_count : integer := 2; -- function declaration function port_to_raw(din : port_struct) return std_logic_vector; function raw_to_port(din : std_logic_vector(71 downto 0)) return port_struct; function fill_port(din : std_logic) return port_struct; end bus_package; package body bus_package is function port_to_raw(din : port_struct) return std_logic_vector is variable result : std_logic_vector(71 downto 0); begin result := din.data & din.address & din.we & din.dmode & din.id; return result; end; function raw_to_port(din : std_logic_vector(71 downto 0)) return port_struct is variable result : port_struct; begin result.data := din(71 downto 40); result.address := din(39 downto 8); result.we := din(7); result.dmode := din(6); result.id := din(5 downto 0); return result; end; function fill_port(din : std_logic) return port_struct is variable result : port_struct; begin result.data := (others => din); result.address := (others => din); result.we := din; result.dmode := din; result.id := (others => din); return result; end; end package body;