library ieee; use work.hcore_package.all; use work.bus_package.all; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity hcore_data_id_gen is port ( -- global clk : in std_logic; reset : in std_logic; -- hcores ids : out use_id_t ); end entity; architecture rtl of hcore_data_id_gen is -- function init_ids return use_id_t is variable tmp : use_id_t := (others => 0); begin for i in 0 to hcore_count-1 loop tmp(i) := i; end loop; return tmp; end; signal use_id : use_id_t := init_ids; signal delay_count : std_logic_vector(5 downto 0) := (others => '0'); -- begin process(clk) begin if rising_edge(clk) then if reset = '1' then delay_count <= (others => '0'); for i in 0 to hcore_count-1 loop use_id(i) <= i; end loop; else if delay_count = "000000" then use_id(hcore_count-1) <= use_id(0); for i in 1 to hcore_count-1 loop use_id(i-1) <= use_id(i); end loop; end if; delay_count <= delay_count + 1; end if; end if; end process; ids <= use_id; end rtl;