LIBRARY ieee; USE ieee.std_logic_1164.all; use IEEE.MATH_REAL.ALL; LIBRARY altera_mf; USE altera_mf.all; ENTITY sc_fifo_usedw IS GENERIC ( FIFO_DEPTH : natural; FIFO_WIDTH : natural; FIFO_SHOWAHEAD : string; FIFO_USERAM : string; FIFO_USEDWWIDTH : natural ); PORT ( clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (FIFO_WIDTH-1 DOWNTO 0); rdreq : IN STD_LOGIC ; sclr : IN STD_LOGIC ; wrreq : IN STD_LOGIC ; empty : OUT STD_LOGIC ; full : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (FIFO_WIDTH-1 DOWNTO 0); usedw : OUT STD_LOGIC_VECTOR (FIFO_USEDWWIDTH-1 DOWNTO 0) ); END sc_fifo_usedw; ARCHITECTURE rtl OF sc_fifo_usedw IS COMPONENT scfifo GENERIC ( add_ram_output_register : STRING; intended_device_family : STRING; lpm_numwords : NATURAL; lpm_showahead : STRING; lpm_type : STRING; lpm_width : NATURAL; lpm_widthu : NATURAL; overflow_checking : STRING; underflow_checking : STRING; use_eab : STRING ); PORT ( clock : IN STD_LOGIC ; data : IN STD_LOGIC_VECTOR (FIFO_WIDTH-1 DOWNTO 0); rdreq : IN STD_LOGIC ; sclr : IN STD_LOGIC ; empty : OUT STD_LOGIC ; full : OUT STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (FIFO_WIDTH-1 DOWNTO 0); wrreq : IN STD_LOGIC ; usedw : OUT STD_LOGIC_VECTOR (FIFO_USEDWWIDTH-1 DOWNTO 0) ); END COMPONENT; BEGIN scfifo_component : scfifo GENERIC MAP ( add_ram_output_register => "OFF", intended_device_family => "Cyclone IV E", lpm_numwords => FIFO_DEPTH, lpm_showahead => FIFO_SHOWAHEAD, lpm_type => "scfifo", lpm_width => FIFO_WIDTH, lpm_widthu => FIFO_USEDWWIDTH, overflow_checking => "OFF", underflow_checking => "OFF", use_eab => FIFO_USERAM ) PORT MAP ( clock => clock, data => data, rdreq => rdreq, sclr => sclr, wrreq => wrreq, empty => empty, full => full, q => q, usedw => usedw ); END rtl;