org hcoreStartPc .def srRegOffset 3 nop nop nop nop nop ;preload gssr r127,0 ;get core number cmpeq last,0 br.tc notCoreZero nop ;delay slot nop ;delay slot nop ;delay slot nop ;delay slot nop ;delay slot ; move hold,source moveh hold,last,>>source or r16,last,0 ;source ;set regoffset default move hold,0 sssr last,srRegOffset ;set r0 as rotate move hold,0 ;r0 roe last,1 ;enable ;load [source]++ into r0-r15 move r18,15 ;count readLoop nop ld r0,r16,0 add r16,r16,2 cmpeq r18,0 br.tc readLoop gssr hold,srRegOffset ;delay slot add hold,last,1 ;delay slot sssr last,srRegOffset ;delay slot at 4th cycle is valid sub r18,r18,1 ;delay slot nop ;delay slot ; ;unset r0 as rotate move hold,0 ;r0 roe last,0 ;enable notCoreZero br notCoreZero nop nop nop nop nop source word $00000000 word $00000001 word $00000002 word $00000003 word $00000004 word $00000005 word $00000006 word $00000007 word $00000008 word $00000009 word $0000000a word $0000000b word $0000000c word $0000000d word $0000000e word $0000000f